DDRC QOS参数及相关寄存器说明

QOS参数格式

binfo_default.json文件中存在qos参数格式及默认值。其中qos_common是通用参数,qos_read是读方向的参数,qos_write是写方向的参数。read/write的相关参数可支持每个AXI port单独配置,以rqos_map_region1为例说明参数和每个AXI port的对应关系:

“rqos_map_region1” : [1, 1, 1, 1, 1]

=>

“rqos_map_region1” : [port0, port1, port2, port3, port4]

其余read/write参数的对应关系类似。另外AXI port和J5 subsys之间的对应关系如下表所示:

port和subsys之间的对应关系

Port num

Port0

Port1

Port2

Port3(APV)

Port4

Sys Name

CPU SYS

BPU SYS

CVSYS

AONSYS/PERISYS/VIDEOSYS

CAMERSYS

qos参数格式及默认值:

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在J5 DDRC的硬件配置中, rqos_map_region2和rqos_map_level2参数为resreved的,调试过程中应选择忽略。其余参数的详细说明参考 相关寄存器说明 章节。

相关寄存器说明

qos参数涉及的寄存器信息描述如下,包括寄存器的偏移地址,参数含义表述以及参数有效值范围说明。参数lpr_num_entires描述中的MEMC_NO_OF_ENTRY为64。J5芯片内部有两个DDRC,寄存器的偏移地址都一样,但基地址不一样,DDRC0的寄存器基地址为0x4D000000,DDRC1的寄存器基地址为0x4F000000。

Register Name

Offset

Bits

Field Name

Description

SCHED

0x250

13:8

lpr_num_entires

Number of entries in the low priority transaction store is this value + 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries +1)) is the number of entries available for the high priority transaction store. Setting this to maximum value allocates all entries to low priority transaction store. Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high priority transaction store.

Note: In ECC configurations, the numbers of write and low priority read credits issued is one less than in the non-ECC case. One entry each is reserved in the write and low-priority read CAMs for storing the RMW requests arising out of single bit error correction RMW operation.

Valid Value:0 ~ 63

Register Name

Offset

Bits

Field Name

Description

PERHPR1

0x25C

31:24

hpr_xact_run_length

Indicates the number of transactions that are serviced once the HPR queue goes critical is the smaller of:

■ (a) This number

■ (b) Number of transactions available

Unit: Transaction

Valid Value:0 ~ 255

23:16

Reserved Filed

15:0

hpr_max_starve

Indicates the number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1.

Programming it to 0x0 disables the starvation functionality.

During normal operation, this function must not be disabled as it causes excessive latencies.

Valid Value:0 ~ 65535

Register Name

Offset

Bits

Field Name

Description

PERLPR1

0x264

31:24

lpr_xact_run_length

Indicates the number of transactions that are serviced once the LPR queue goes critical is the smaller of:

■ (a) This number

■ (b) Number of transactions available

Unit: Transaction

Valid Value:0 ~ 255

23:16

Reserved Filed

15:0

lpr_max_starve

Indicates the number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1.

Programming it to 0x0 disables the starvation functionality.

During normal operation, this function must not be disabled as it causes excessive latencies.

Valid Value:0 ~ 65535

Register Name

Offset

Bits

Field Name

Description

PERWR1

0x26C

31:24

w_xact_run_length

Indicates the number of transactions that are serviced once the WR queue goes critical is the smaller of:

■ (a) This number

■ (b) Number of transactions available

Unit: Transaction

Valid Value:0 ~ 255

23:16

Reserved Filed

15:0

w_max_starve

Indicates the number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality. During normal operation, this function must not be disabled as it causes excessive latencies.Valid Value:0 ~ 65535

Register Name

Offset

Bits

Field Name

Description

PCFGQOS0_n(for n=0;n<=4)

0x494+0xB0*n

31:22

Reserved Filed

21:20

rqos_map_region1

This bit field indicates the traffic class of region1. Valid values are:

■ 0 - LPR

■ 1 - VPR

■ 2 - HPR

19:18

Reserved Filed

17:16

rqos_map_region0

This bit field indicates the traffic class of region 0. Valid values are:

■ 0 - LPR

■ 1 - VPR

■ 2 - HPR

15:4

Reserved Filed

3:0

rqos_map_level1

Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which corresponds to arqos.

Note that for PA, arqos values are used directly as port priorities, where the higher the value corresponds to the higher port priority.

All the map_level* registers must be set to distinct values

Register Name

Offset

Bits

Field Name

Description

PCFGQOS1_n(for n=0;n<=4)

0x498+0xB0*n

31:27

Reserved Filed

26:16

rqos_map_timeoutr

Specifies the timeout value for transactions mapped to the red address queue.

Valid Value:0 ~ 2047

15:11

Reserved Filed

10:0

rqos_map_timeoutb

Specifies the timeout value for transactions mapped to the blue address queue.

Valid Value:0 ~ 2047

Register Name

Offset

Bits

Field Name

Description

PCFGWQOS0_n(for n=0;n<=4)

0x49C+0xB0*n

31:26

Reserved Filed

25:24

wrqos_map_region2

This bit field indicates the traffic class of region 2. Valid values are:

■ 0 - NPW

■ 1 - VPW

23:22

Reserved Filed

21:20

wqos_map_region1

This bit field indicates the traffic class of region 1. Valid values are:

■ 0 - NPW

■ 1 - VPW

19:18

Reserved Filed

17:16

wqos_map_region0

This bit field indicates the traffic class of region 0. Valid values are:

■ 0 - NPW

■ 1 - VPW

15:12

Reserved Filed

11:8

wqos_map_level2

Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1).

Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos.

Region2 starts from (level2 + 1) up to 15.

Note that for PA, awqos values are used directly as port priorities, where the higher the value corresponds to the higher port priority.

All the map_level* registers must be set to distinct values.

7:4

Reserved Filed

3:0

wqos_map_level1

Separation level indicating the end of region0 mapping; start of region0 is 0.

Possible values for level1 are 0 to 13 which corresponds to awqos.

Note that for PA, awqos values are used directly as port priorities, where the higher the value corresponds to the higher port priority.

All of the map_level* registers must be set to distinct values.

Register Name

Offset

Bits

Field Name

Description

PCFGWQOS1_n(for n=0;n<=4)

0x498+0xB0*n

31:27

Reserved Filed

26:16

wqos_map_timeout2

Specifies the timeout value for write transactions in region2.

Valid Value:0 ~ 2047

15:11

Reserved Filed

10:0

wqos_map_timeout1

Specifies the timeout value for write transactions in region 0 and 1.

Valid Value:0 ~ 2047